FIFO memories have numerous applications in electronic circuits and systems. In many cases, a FIFO memory serves as a buffer between two portions of an electronic circuit or system which operate asynchronously to one another. In this case, data words are simultaneously written into the FIFO at one rate and read out of the FIFO at a different rate.
It is important to be able to determine the current occupancy level of the FIFO. One prior art technique for doing this is to use an up-down counter. The counter counts up when a word is written into the FIFO, counts down when a word is read from the FIFO, and remains unchanged when a read and write occur simultaneously. In this case, the current count is the current occupancy level. However, to implement this technique read and write events must be synchronized to the same clock. When the read and write clock are asynchronous, yet have similar frequencies (e.g., less 2:1 ratio), this technique is no longer useful.
Another way to determine the occupancy level of the FIFO is to subtract the read address (i.e., the read pointer) from the write address (i.e., the write pointer). However, in order for the subtraction to have meaning, the read and write addresses are generally required to be stable values and to be synchronized to the same clock. These criteria (stability and synchronization to the same clock) are not always easy to achieve.
Another problem affecting FIFO performance is that in an asynchronous circuit, unpredictable gate delays may affect circuit functionality. In many cases, delay matching may be used to control when particular signals occur. However, in the case of an integrated circuit generated using automatic place and route tools (e.g. standard cell designs or gate arrays), it is not feasible to use delay matching to control when signals occur. Thus, the reliability of a FIFO incorporated in an asynchronous integrated circuit formed from standard cells may be impacted by unpredictable gate delays.
Accordingly, it is an object of the present invention to provide a FIFO which overcomes the prior art problems discussed above.
Specifically, it is an object of the invention to provide a FIFO in which the read clock and write clock are asynchronous to one another and in which the FIFO level is obtained by subtracting read and write addresses which are synchronized to the same clock.
It is also an object of the invention to provide a FIFO which is unaffected by unpredictable gate delays.